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Searched refs:cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h557 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 … macro
H A Dnbio_7_0_offset.h1029 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 … macro