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/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_afmt.c51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
95 if (amdgpu_afmt_predefined_acr[i].clock == clock) in amdgpu_afmt_acr()
100 amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); in amdgpu_afmt_acr()
101 amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); in amdgpu_afmt_acr()
102 amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); in amdgpu_afmt_acr()
H A Datombios_crtc.c316 u32 dp_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
317 u32 clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll() local
364 clock = (clock * 5) / 4; in amdgpu_atombios_crtc_adjust_pll()
367 clock = (clock * 3) / 2; in amdgpu_atombios_crtc_adjust_pll()
370 clock = clock * 2; in amdgpu_atombios_crtc_adjust_pll()
581 u32 clock, in amdgpu_atombios_crtc_program_pll() argument
710 (clock > 165000)) in amdgpu_atombios_crtc_program_pll()
790 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
797 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
804 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
[all …]
H A Damdgpu_atombios.c612 adev->clock.ppll[i] = *ppll; in amdgpu_atombios_get_clock_info()
660 adev->clock.default_sclk = in amdgpu_atombios_get_clock_info()
662 adev->clock.default_mclk = in amdgpu_atombios_get_clock_info()
674 adev->clock.default_dispclk = in amdgpu_atombios_get_clock_info()
680 adev->clock.default_dispclk = 60000; in amdgpu_atombios_get_clock_info()
684 adev->clock.default_dispclk = 62500; in amdgpu_atombios_get_clock_info()
686 adev->clock.dp_extclk = in amdgpu_atombios_get_clock_info()
688 adev->clock.current_dispclk = adev->clock.default_dispclk; in amdgpu_atombios_get_clock_info()
881 int id, u32 clock) in amdgpu_atombios_get_asic_ss_info() argument
997 u32 clock, in amdgpu_atombios_get_clock_dividers() argument
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/dragonfly/sys/dev/drm/radeon/
H A Dradeon_clocks.c38 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock()
68 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock()
144 rdev->clock.max_pixel_clock = 35000; in radeon_read_clocks_OF()
153 rdev->clock.default_sclk = (*val) / 10; in radeon_read_clocks_OF()
155 rdev->clock.default_sclk = in radeon_read_clocks_OF()
160 rdev->clock.default_mclk = (*val) / 10; in radeon_read_clocks_OF()
162 rdev->clock.default_mclk = in radeon_read_clocks_OF()
224 rdev->clock.max_pixel_clock = 35000; in radeon_get_clock_info()
267 rdev->clock.default_sclk = in radeon_get_clock_info()
269 rdev->clock.default_mclk = in radeon_get_clock_info()
[all …]
H A Dradeon_audio.c73 struct radeon_crtc *crtc, unsigned int clock);
75 struct radeon_crtc *crtc, unsigned int clock);
77 struct radeon_crtc *crtc, unsigned int clock);
79 struct radeon_crtc *crtc, unsigned int clock);
81 struct radeon_crtc *crtc, unsigned int clock);
83 struct radeon_crtc *crtc, unsigned int clock);
508 radeon_encoder->audio->set_dto(rdev, crtc, clock); in radeon_audio_set_dto()
566 cts = clock * 1000; in radeon_audio_calc_cts()
618 if (hdmi_predefined_acr[i].clock == clock) in radeon_audio_acr()
721 radeon_audio_set_dto(encoder, mode->clock); in radeon_audio_hdmi_mode_set()
[all …]
H A Datombios_crtc.c566 u32 dp_clock = mode->clock; in atombios_adjust_pll()
567 u32 clock = mode->clock; in atombios_adjust_pll() local
660 clock = (clock * 5) / 4; in atombios_adjust_pll()
663 clock = (clock * 3) / 2; in atombios_adjust_pll()
666 clock = clock * 2; in atombios_adjust_pll()
825 u32 clock, in atombios_crtc_program_pll() argument
1068 u32 clock = mode->clock; in atombios_crtc_set_pll() local
1081 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1084 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1089 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
[all …]
H A Ddce6_afmt.c282 struct radeon_crtc *crtc, unsigned int clock);
284 struct radeon_crtc *crtc, unsigned int clock) in dce6_hdmi_audio_set_dto() argument
299 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce6_hdmi_audio_set_dto()
303 struct radeon_crtc *crtc, unsigned int clock);
305 struct radeon_crtc *crtc, unsigned int clock) in dce6_dp_audio_set_dto() argument
327 clock = clock * 100 / div; in dce6_dp_audio_set_dto()
330 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); in dce6_dp_audio_set_dto()
333 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce6_dp_audio_set_dto()
H A Devergreen_hdmi.c243 struct radeon_crtc *crtc, unsigned int clock);
245 struct radeon_crtc *crtc, unsigned int clock) in dce4_hdmi_audio_set_dto() argument
247 unsigned int max_ratio = clock / 24000; in dce4_hdmi_audio_set_dto()
284 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce4_hdmi_audio_set_dto()
288 struct radeon_crtc *crtc, unsigned int clock);
290 struct radeon_crtc *crtc, unsigned int clock) in dce4_dp_audio_set_dto() argument
318 clock = 100 * clock / div; in dce4_dp_audio_set_dto()
322 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce4_dp_audio_set_dto()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu8_hwmgr.c69 uint32_t clock, uint32_t msg) in smu8_get_eclk_level() argument
100 uint32_t clock, uint32_t msg) in smu8_get_sclk_level() argument
130 uint32_t clock, uint32_t msg) in smu8_get_uvd_level() argument
559 unsigned long clock = 0, level; in smu8_init_sclk_limit() local
585 unsigned long clock = 0, level; in smu8_init_uvd_limit() local
612 unsigned long clock = 0, level; in smu8_init_vce_limit() local
639 unsigned long clock = 0, level; in smu8_init_acp_limit() local
684 unsigned long clock = 0; in smu8_update_sclk_limit() local
698 if (clock == 0) in smu8_update_sclk_limit()
722 clock = stable_pstate_sclk; in smu8_update_sclk_limit()
[all …]
/dragonfly/sys/dev/drm/i915/
H A Dintel_dpll_mgr.c557 switch (clock) { in hsw_wrpll_get_budget_for_freq()
695 freq2k = clock / 100; in hsw_ddi_calculate_wrpll()
783 switch (clock / 2) { in hsw_ddi_dp_get_dpll()
1289 int clock) in skl_ddi_hdmi_pll_dividers() argument
1335 switch (clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
1647 int clock; member
1706 if (bxt_dp_clk_val[i].clock == clock) { in bxt_ddi_dp_pll_dividers()
1744 if (clock > 270000) in bxt_ddi_set_dpll_hw_state()
1748 else if (clock > 67000) in bxt_ddi_set_dpll_hw_state()
2266 int clock) in cnl_ddi_hdmi_pll_dividers() argument
[all …]
H A Dintel_display.c510 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
511 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
528 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
539 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
540 clock->p = clock->p1 * clock->p2; in vlv_calc_dpll_params()
551 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
552 clock->p = clock->p1 * clock->p2; in chv_calc_dpll_params()
871 clock.p = clock.p1 * clock.p2; in vlv_find_best_dpll()
[all …]
/dragonfly/sys/dev/disk/sdhci/
H A Dsdhci.c176 uint32_t clock; in sdhci_reset() local
187 clock = slot->clock; in sdhci_reset()
188 slot->clock = 0; in sdhci_reset()
193 slot->clock = 0; in sdhci_reset()
261 if (clock == slot->clock) in sdhci_set_clock()
263 slot->clock = clock; in sdhci_set_clock()
269 if (clock == 0) in sdhci_set_clock()
296 if (res <= clock) in sdhci_set_clock()
1903 clock = max_clock; in sdhci_generic_write_ivar()
1910 clock >>= 1; in sdhci_generic_write_ivar()
[all …]
/dragonfly/share/syscons/keymaps/
H A Dus.emacs.kbd65 058 clock clock clock clock clock clock clock clock O
H A Dru.koi8-r.win.kbd65 058 clock clock clock clock clock clock clock clock O
193 186 clock clock clock clock clock clock clock clock O
H A Del.iso07.kbd111 058 clock clock clock clock clock clock clock clock O
224 186 clock clock clock clock clock clock clock clock O
H A Dru.cp866.kbd65 058 alock clock clock clock clock clock clock clock O
194 186 alock clock clock clock clock clock clock clock O
H A Dru.koi8-r.kbd65 058 alock clock clock clock clock clock clock clock O
193 186 alock clock clock clock clock clock clock clock O
H A Dru.koi8-r.shift.kbd65 058 alock clock clock clock clock clock clock clock O
193 186 alock clock clock clock clock clock clock clock O
H A Dgr.elot.acc.kbd68 058 clock clock clock clock clock clock clock clock O
198 186 clock clock clock clock clock clock clock clock O
H A Dgr.us101.acc.kbd68 058 clock clock clock clock clock clock clock clock O
198 186 clock clock clock clock clock clock clock clock O
H A Dlt.iso4.kbd65 058 clock clock clock clock clock clock clock clock O
193 186 clock clock clock clock clock clock clock clock O
H A Dus.dvorak.kbd5 # esc <-> `~, clock <-> lctrl, and =+ <-> \| (supplied as
74 058 clock clock clock clock clock clock clock clock O
H A Dnorwegian.iso.kbd65 058 clock clock clock clock clock clock clock clock O
/dragonfly/sys/dev/drm/
H A Ddrm_modes.c324 drm_mode->clock = tmp; in drm_cvt_mode()
515 drm_mode->clock = pixel_freq; in drm_gtf_mode_complex()
781 calc_val = (mode->clock * 1000); in drm_mode_vrefresh()
836 p->crtc_clock = p->clock; in drm_mode_set_crtcinfo()
960 if (mode1->clock && mode2->clock) { in drm_mode_equal()
961 if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock)) in drm_mode_equal()
963 } else if (mode1->clock != mode2->clock) in drm_mode_equal()
1036 if (mode->clock == 0) in drm_mode_validate_basic()
1230 diff = b->clock - a->clock; in drm_mode_compare()
1535 out->clock = in->clock; in drm_mode_convert_to_umode()
[all …]
/dragonfly/contrib/ldns/
H A Dutil.c275 ldns_gmtime64_r(int64_t clock, struct tm *result) in ldns_gmtime64_r() argument
278 result->tm_sec = (int) LDNS_MOD(clock, 60); in ldns_gmtime64_r()
279 clock = LDNS_DIV(clock, 60); in ldns_gmtime64_r()
280 result->tm_min = (int) LDNS_MOD(clock, 60); in ldns_gmtime64_r()
281 clock = LDNS_DIV(clock, 60); in ldns_gmtime64_r()
282 result->tm_hour = (int) LDNS_MOD(clock, 24); in ldns_gmtime64_r()
283 clock = LDNS_DIV(clock, 24); in ldns_gmtime64_r()
285 ldns_year_and_yday_from_days_since_epoch(clock, result); in ldns_gmtime64_r()

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