Searched refs:ctrl1 (Results 1 – 3 of 3) sorted by relevance
927 val |= pll->state.hw_state.ctrl1 << (pll->id * 6); in skl_ddi_pll_write_ctrl1()997 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()1031 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()1291 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local1298 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_hdmi_pll_dividers()1300 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); in skl_ddi_hdmi_pll_dividers()1318 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()1328 uint32_t ctrl1; in skl_ddi_dp_set_dpll_hw_state() local1334 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_dp_set_dpll_hw_state()1357 dpll_hw_state->ctrl1 = ctrl1; in skl_ddi_dp_set_dpll_hw_state()[all …]
127 uint32_t ctrl1; member
11292 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); in intel_pipe_config_compare()