Home
last modified time | relevance | path

Searched refs:dispclk_khz (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clocks.c470 new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100; in dce12_update_clocks()
475 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); in dce12_update_clocks()
476 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dce12_update_clocks()
494 bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz; in dcn1_determine_dppclk_threshold()
564 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn1_ramp_up_dispclk_with_dpp()
587 if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz in dcn1_update_clocks()
638 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz) in dcn1_update_clocks()
639 || new_clocks->dispclk_khz == dccg->clks.dispclk_khz) { in dcn1_update_clocks()
641 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn1_update_clocks()
675 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); in dce_update_clocks()
[all …]
/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_hw_sequencer.c162 req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; in dce100_set_bandwidth()
H A Ddce100_resource.c734 context->bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
737 context->bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/core/
H A Ddc_debug.c355 context->bw.dcn.clk.dispclk_khz, in context_clock_trace()
363 context->bw.dcn.clk.dispclk_khz, in context_clock_trace()
H A Ddc_link.c1369 clocks.dispclk_khz = 0; in enable_link_dp()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Dcore_types.h254 int dispclk_khz; member
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c1051 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
1053 context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); in dcn_validate_bandwidth()
1055 if (context->bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1057 context->bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1061 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; in dcn_validate_bandwidth()
1297 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); in dcn_find_dcfclk_suits_all()
H A Ddce_calcs.c2745 if (calcs_output->dispclk_khz > int_max_clk) in is_display_configuration_supported()
3030 calcs_output->dispclk_khz = in bw_calcs()
3555 calcs_output->dispclk_khz = 0; in bw_calcs()
/dragonfly/sys/dev/drm/amd/display/dc/
H A Ddc.h203 int dispclk_khz; member
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c346 dc->current_state->bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
2020 dc->res_pool->dccg->clks.dispclk_khz / 2; in update_dchubp_dpp()
2028 dc->res_pool->dccg->clks.dispclk_khz / 2 : in update_dchubp_dpp()
2029 dc->res_pool->dccg->clks.dispclk_khz; in update_dchubp_dpp()
2242 pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz; in dcn10_pplib_apply_display_requirements()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c2560 pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz; in pplib_apply_display_requirements()
2589 req_clks.dispclk_khz = context->bw.dce.dispclk_khz; in dce110_set_bandwidth()
H A Ddce110_resource.c873 context->bw.dce.dispclk_khz, in dce110_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
H A Ddce112_resource.c828 context->bw.dce.dispclk_khz, in dce112_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/dce80/
H A Ddce80_resource.c742 context->bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()