Searched refs:dispclk_khz (Results 1 – 14 of 14) sorted by relevance
/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_clocks.c | 470 new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100; in dce12_update_clocks() 475 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); in dce12_update_clocks() 476 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dce12_update_clocks() 494 bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz; in dcn1_determine_dppclk_threshold() 564 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn1_ramp_up_dispclk_with_dpp() 587 if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz in dcn1_update_clocks() 638 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz) in dcn1_update_clocks() 639 || new_clocks->dispclk_khz == dccg->clks.dispclk_khz) { in dcn1_update_clocks() 641 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn1_update_clocks() 675 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); in dce_update_clocks() [all …]
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/dragonfly/sys/dev/drm/amd/display/dc/dce100/ |
H A D | dce100_hw_sequencer.c | 162 req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; in dce100_set_bandwidth()
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H A D | dce100_resource.c | 734 context->bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth() 737 context->bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
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/dragonfly/sys/dev/drm/amd/display/dc/core/ |
H A D | dc_debug.c | 355 context->bw.dcn.clk.dispclk_khz, in context_clock_trace() 363 context->bw.dcn.clk.dispclk_khz, in context_clock_trace()
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H A D | dc_link.c | 1369 clocks.dispclk_khz = 0; in enable_link_dp()
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/dragonfly/sys/dev/drm/amd/display/dc/inc/ |
H A D | core_types.h | 254 int dispclk_khz; member
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/dragonfly/sys/dev/drm/amd/display/dc/calcs/ |
H A D | dcn_calcs.c | 1051 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth() 1053 context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); in dcn_validate_bandwidth() 1055 if (context->bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth() 1057 context->bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth() 1061 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; in dcn_validate_bandwidth() 1297 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); in dcn_find_dcfclk_suits_all()
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H A D | dce_calcs.c | 2745 if (calcs_output->dispclk_khz > int_max_clk) in is_display_configuration_supported() 3030 calcs_output->dispclk_khz = in bw_calcs() 3555 calcs_output->dispclk_khz = 0; in bw_calcs()
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/dragonfly/sys/dev/drm/amd/display/dc/ |
H A D | dc.h | 203 int dispclk_khz; member
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hw_sequencer.c | 346 dc->current_state->bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state() 2020 dc->res_pool->dccg->clks.dispclk_khz / 2; in update_dchubp_dpp() 2028 dc->res_pool->dccg->clks.dispclk_khz / 2 : in update_dchubp_dpp() 2029 dc->res_pool->dccg->clks.dispclk_khz; in update_dchubp_dpp() 2242 pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz; in dcn10_pplib_apply_display_requirements()
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/dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
H A D | dce110_hw_sequencer.c | 2560 pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz; in pplib_apply_display_requirements() 2589 req_clks.dispclk_khz = context->bw.dce.dispclk_khz; in dce110_set_bandwidth()
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H A D | dce110_resource.c | 873 context->bw.dce.dispclk_khz, in dce110_validate_bandwidth()
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/dragonfly/sys/dev/drm/amd/display/dc/dce112/ |
H A D | dce112_resource.c | 828 context->bw.dce.dispclk_khz, in dce112_validate_bandwidth()
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/dragonfly/sys/dev/drm/amd/display/dc/dce80/ |
H A D | dce80_resource.c | 742 context->bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()
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