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Searched refs:dlg_otg_param (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c67 if (optc->dlg_otg_param.vstartup_start == 0) { in optc1_program_global_sync()
73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start); in optc1_program_global_sync()
76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, in optc1_program_global_sync()
77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); in optc1_program_global_sync()
80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset); in optc1_program_global_sync()
307 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || in optc1_program_timing()
308 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || in optc1_program_timing()
309 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { in optc1_program_timing()
315 if (optc->dlg_otg_param.vstartup_start > asic_blank_end) in optc1_program_timing()
316 v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end; in optc1_program_timing()
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H A Ddcn10_hw_sequencer.c657 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; in dcn10_enable_stream_timing()
658 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; in dcn10_enable_stream_timing()
659 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; in dcn10_enable_stream_timing()
660 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; in dcn10_enable_stream_timing()
662 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal; in dcn10_enable_stream_timing()
2209 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; in program_all_pipe_in_tree()
2210 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; in program_all_pipe_in_tree()
2211 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; in program_all_pipe_in_tree()
2212 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; in program_all_pipe_in_tree()
2213 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal; in program_all_pipe_in_tree()
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h129 struct _dlg_otg_param dlg_otg_param; member