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Searched refs:doorbell_index (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dnbio_v6_1.c74 bool use_doorbell, int doorbell_index) in nbio_v6_1_sdma_doorbell_range() argument
82 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_sdma_doorbell_range()
118 bool use_doorbell, int doorbell_index) in nbio_v6_1_ih_doorbell_range() argument
123 …h_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_ih_doorbell_range()
H A Dnbio_v7_0.c81 bool use_doorbell, int doorbell_index) in nbio_v7_0_sdma_doorbell_range() argument
93 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_sdma_doorbell_range()
114 bool use_doorbell, int doorbell_index) in nbio_v7_0_ih_doorbell_range() argument
119 …h_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_ih_doorbell_range()
H A Dvega10_ih.c141 OFFSET, adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
150 adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
368 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in vega10_ih_set_rptr()
392 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; in vega10_ih_sw_init()
H A Dtonga_ih.c153 OFFSET, adev->irq.ih.doorbell_index); in tonga_ih_irq_init()
295 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in tonga_ih_set_rptr()
325 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH; in tonga_ih_sw_init()
H A Damdgpu_ih.h56 u32 doorbell_index; member
H A Dvce_v4_0.c109 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
178 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
469 ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2; in vce_v4_0_sw_init()
471 ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1; in vce_v4_0_sw_init()
H A Dsdma_v4_0.c345 ring->doorbell_index, ring->wptr << 2); in sdma_v4_0_ring_set_wptr()
346 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v4_0_ring_set_wptr()
679 OFFSET, ring->doorbell_index); in sdma_v4_0_gfx_resume()
686 ring->doorbell_index); in sdma_v4_0_gfx_resume()
1260 ring->doorbell_index = (i == 0) ? in sdma_v4_0_sw_init()
H A Damdgpu_ring.h200 u32 doorbell_index; member
H A Damdgpu_gfx.c217 ring->doorbell_index = AMDGPU_DOORBELL_KIQ; in amdgpu_gfx_kiq_init_ring()
H A Duvd_v7_0.c157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
473 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; in uvd_v7_0_sw_init()
475 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; in uvd_v7_0_sw_init()
744 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); in uvd_v7_0_mmsch_start()
H A Dgfx_v9_0.c1463 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; in gfx_v9_0_compute_ring_init()
1557 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; in gfx_v9_0_sw_init()
2499 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_cp_gfx_resume()
2508 DOORBELL_RANGE_LOWER, ring->doorbell_index); in gfx_v9_0_cp_gfx_resume()
2658 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx_v9_0_kiq_kcq_enable()
2724 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_mqd_init()
2790 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v9_0_mqd_init()
3201 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); in gfx_v9_0_kcq_disable()
3878 WDOORBELL64(ring->doorbell_index, ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
4143 WDOORBELL64(ring->doorbell_index, ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
H A Dsdma_v3_0.c391 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
703 OFFSET, ring->doorbell_index); in sdma_v3_0_gfx_resume()
1208 ring->doorbell_index = (i == 0) ? in sdma_v3_0_sw_init()
H A Damdgpu.h1278 bool use_doorbell, int doorbell_index);
1284 bool use_doorbell, int doorbell_index);
H A Dgfx_v8_0.c2003 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; in gfx_v8_0_compute_ring_init()
2119 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; in gfx_v8_0_sw_init()
4447 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v8_0_set_cpg_door_bell()
4659 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) | in gfx_v8_0_kiq_kcq_enable()
4793 DOORBELL_OFFSET, ring->doorbell_index); in gfx_v8_0_mqd_init()
5122 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); in gfx_v8_0_kcq_disable()
6307 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6495 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_compute()
/dragonfly/sys/dev/drm/radeon/
H A Dcik.c4221 WDOORBELL32(ring->doorbell_index, ring->wptr); in cik_compute_set_wptr()
4740 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index); in cik_cp_compute_resume()
8614 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8621 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
H A Dradeon.h874 u32 doorbell_index; member