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Searched refs:dpp_per_plane (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calc_auto.c1013 v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k]; in display_pipe_configuration()
1112 v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k]; in display_pipe_configuration()
1115 v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k]; in display_pipe_configuration()
1181 …ax2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] … in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1182 …ax2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] … in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1226 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1229 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1263 v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1265 v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1619 if (v->dpp_per_plane[k] > 1.0) { in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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H A Ddcn_calcs.c1092 …pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2… in dcn_validate_bandwidth()
1093 …pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] ==… in dcn_validate_bandwidth()
1094 …pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2… in dcn_validate_bandwidth()
1122 if (v->dpp_per_plane[input_idx] == 2 || in dcn_validate_bandwidth()
1133 …hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_id… in dcn_validate_bandwidth()
1134 …hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_… in dcn_validate_bandwidth()
1135 …hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_id… in dcn_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Ddcn_calcs.h221 float dpp_per_plane[number_of_planes_minus_one + 1]; member