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Searched refs:f32_cntl (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsdma_v3_0.c553 u32 f32_cntl, phase_quantum = 0; in sdma_v3_0_ctx_switch_enable() local
581 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
600 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
614 u32 f32_cntl; in sdma_v3_0_enable() local
625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
627 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v3_0_enable()
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H A Dsdma_v4_0.c540 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable() local
568 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v4_0_ctx_switch_enable()
569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
579 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v4_0_ctx_switch_enable()
594 u32 f32_cntl; in sdma_v4_0_enable() local
603 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v4_0_enable()
604 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
605 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v4_0_enable()
H A Dsdma_v2_4.c378 u32 f32_cntl; in sdma_v2_4_enable() local
387 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
389 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
391 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
392 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()