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Searched refs:g4x (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_pm.c453 dev_priv->wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
1348 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1357 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1369 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1539 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1554 intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
5569 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
5578 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
5592 crtc_state->wm.g4x.intermediate = in g4x_wm_sanitize()
5593 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
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H A Dintel_drv.h596 } g4x; member
824 struct g4x_wm_state g4x; member
H A Di915_drv.h2543 struct g4x_wm_values g4x; member