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Searched refs:gfx (Results 1 – 25 of 40) sorted by relevance

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/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_gfx.c45 i = ffs(adev->gfx.scratch.free_mask); in amdgpu_gfx_scratch_get()
65 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
125 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_multipipe_capable()
137 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
139 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
142 if (mec >= adev->gfx.mec.num_mec) in amdgpu_gfx_compute_queue_acquire()
157 adev->gfx.num_compute_rings = in amdgpu_gfx_compute_queue_acquire()
172 queue_bit = adev->gfx.mec.num_mec in amdgpu_gfx_kiq_acquire()
281 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_compute_mqd_sw_init()
304 ring = &adev->gfx.compute_ring[i]; in amdgpu_gfx_compute_mqd_sw_init()
[all …]
H A Dgfx_v9_0.c302 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
450 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
452 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
454 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
597 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v9_0_init_microcode()
1589 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
1647 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v9_0_sw_fini()
2261 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
2341 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
2545 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
[all …]
H A Dgfx_v8_0.c830 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
946 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
948 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
1120 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1930 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
2154 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2207 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v8_0_sw_fini()
4209 if (!adev->gfx.rlc_fw) in gfx_v8_0_rlc_load_microcode()
4295 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v8_0_cp_gfx_load_microcode()
4549 if (!adev->gfx.mec_fw) in gfx_v8_0_cp_compute_load_microcode()
[all …]
H A Damdgpu_gfx.h68 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_queue_to_bit()
69 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_queue_to_bit()
70 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_queue_to_bit()
79 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_bit_to_queue()
80 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_queue()
81 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_queue()
82 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_queue()
83 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_bit_to_queue()
90 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
H A Damdgpu_kms.c184 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
188 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
192 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
196 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
200 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
204 fw_info->ver = adev->gfx.rlc_srlg_fw_version; in amdgpu_firmware_info()
213 fw_info->ver = adev->gfx.mec_fw_version; in amdgpu_firmware_info()
216 fw_info->ver = adev->gfx.mec2_fw_version; in amdgpu_firmware_info()
593 adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
626 sizeof(adev->gfx.cu_info.bitmap)); in amdgpu_info_ioctl()
[all …]
H A Damdgpu_debugfs.c486 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
487 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
488 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
491 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
492 config[no_regs++] = adev->gfx.config.max_gs_threads; in amdgpu_debugfs_gca_config_read()
503 config[no_regs++] = adev->gfx.config.num_gpus; in amdgpu_debugfs_gca_config_read()
505 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; in amdgpu_debugfs_gca_config_read()
507 config[no_regs++] = adev->gfx.config.num_rbs; in amdgpu_debugfs_gca_config_read()
641 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_wave_read()
719 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gpr_read()
[all …]
H A Damdgpu_atomfirmware.c345 adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se; in amdgpu_atomfirmware_get_gfx_info()
346 adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
347 adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
348 adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se; in amdgpu_atomfirmware_get_gfx_info()
349 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs; in amdgpu_atomfirmware_get_gfx_info()
350 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
351 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
352 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
353 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
355 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
[all …]
H A Damdgpu_amdkfd.c158 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
169 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
173 if (adev->gfx.kiq.ring.ready) in amdgpu_amdkfd_device_init()
175 adev->gfx.kiq.ring.me - 1, in amdgpu_amdkfd_device_init()
176 adev->gfx.kiq.ring.pipe, in amdgpu_amdkfd_device_init()
177 adev->gfx.kiq.ring.queue), in amdgpu_amdkfd_device_init()
183 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
184 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
399 if (adev->gfx.funcs->get_gpu_clock_counter) in get_gpu_clock_counter()
420 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; in get_cu_info()
[all …]
H A Damdgpu_amdkfd_gfx_v9.c160 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in amdgpu_amdkfd_get_tile_config()
162 adev->gfx.config.macrotile_mode_array; in amdgpu_amdkfd_get_tile_config()
164 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in amdgpu_amdkfd_get_tile_config()
356 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
357 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
418 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hqd_load()
419 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hqd_load()
845 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in invalidate_tlbs_with_kiq()
847 spin_lock(&adev->gfx.kiq.ring_lock); in invalidate_tlbs_with_kiq()
857 spin_unlock(&adev->gfx.kiq.ring_lock); in invalidate_tlbs_with_kiq()
[all …]
H A Damdgpu_amdkfd_gfx_v8.c123 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in get_tile_config()
125 adev->gfx.config.macrotile_mode_array; in get_tile_config()
127 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in get_tile_config()
280 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
332 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hqd_load()
786 adev->gfx.pfp_fw->data; in get_fw_version()
791 adev->gfx.me_fw->data; in get_fw_version()
796 adev->gfx.ce_fw->data; in get_fw_version()
801 adev->gfx.mec_fw->data; in get_fw_version()
806 adev->gfx.mec2_fw->data; in get_fw_version()
[all …]
H A Damdgpu_cgs.c172 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
175 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
178 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
181 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
184 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
187 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
190 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
H A Damdgpu_queue_mgr.c71 *out_ring = &adev->gfx.gfx_ring[ring]; in amdgpu_identity_map()
74 *out_ring = &adev->gfx.compute_ring[ring]; in amdgpu_identity_map()
237 ip_num_rings = adev->gfx.num_gfx_rings; in amdgpu_queue_mgr_map()
240 ip_num_rings = adev->gfx.num_compute_rings; in amdgpu_queue_mgr_map()
H A Damdgpu_ucode.c370 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
371 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, in amdgpu_ucode_init_single_fw()
374 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
375 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, in amdgpu_ucode_init_single_fw()
378 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
379 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, in amdgpu_ucode_init_single_fw()
H A Damdgpu_ctx.c92 if (ring == &adev->gfx.kiq.ring) in amdgpu_ctx_init()
179 if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring) in amdgpu_ctx_do_release()
466 if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring) in amdgpu_ctx_mgr_entity_flush()
491 if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring) in amdgpu_ctx_mgr_entity_fini()
H A Damdgpu_device.c1437 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); in amdgpu_device_parse_gpu_info_fw()
1441 adev->gfx.config.max_texture_channel_caches = in amdgpu_device_parse_gpu_info_fw()
1443 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); in amdgpu_device_parse_gpu_info_fw()
1447 adev->gfx.config.double_offchip_lds_buf = in amdgpu_device_parse_gpu_info_fw()
1449 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); in amdgpu_device_parse_gpu_info_fw()
1450 adev->gfx.cu_info.max_waves_per_simd = in amdgpu_device_parse_gpu_info_fw()
1452 adev->gfx.cu_info.max_scratch_slots_per_cu = in amdgpu_device_parse_gpu_info_fw()
1454 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); in amdgpu_device_parse_gpu_info_fw()
2358 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in amdgpu_device_init()
2384 lockinit(&adev->gfx.gpu_clock_mutex, "agggcm", 0, LK_CANRECURSE); in amdgpu_device_init()
[all …]
H A Dcik.c1037 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in cik_get_register_value()
1039 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in cik_get_register_value()
1041 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in cik_get_register_value()
1043 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in cik_get_register_value()
1061 return adev->gfx.config.gb_addr_config; in cik_get_register_value()
1063 return adev->gfx.config.mc_arb_ramcfg; in cik_get_register_value()
1097 return adev->gfx.config.tile_mode_array[idx]; in cik_get_register_value()
1115 return adev->gfx.config.macrotile_mode_array[idx]; in cik_get_register_value()
H A Dvi.c561 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in vi_get_register_value()
563 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in vi_get_register_value()
565 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in vi_get_register_value()
567 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in vi_get_register_value()
585 return adev->gfx.config.gb_addr_config; in vi_get_register_value()
587 return adev->gfx.config.mc_arb_ramcfg; in vi_get_register_value()
621 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
639 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
H A Duvd_v5_0.c282 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
283 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
284 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
H A Damdgpu_virt.c145 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_rreg()
199 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_wreg()
H A Damdgpu_ucode.h166 struct gfx_firmware_header_v1_0 gfx; member
H A Damdgpu_atombios.c724 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; in amdgpu_atombios_get_gfx_info()
725 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
726 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; in amdgpu_atombios_get_gfx_info()
727 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
728 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
729 adev->gfx.config.max_texture_channel_caches = in amdgpu_atombios_get_gfx_info()
H A Damdgpu_ib.c368 if (ring == &adev->gfx.gfx_ring[0]) { in amdgpu_ib_ring_tests()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_powertune.c943 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_enable_cac_driving_se_didt_config()
968 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_cac_driving_se_didt_config()
977 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_disable_cac_driving_se_didt_config()
981 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_cac_driving_se_didt_config()
1013 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_psm_gc_didt_config()
1034 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_psm_gc_didt_config()
1076 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_se_edc_config()
1089 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_se_edc_config()
1124 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_psm_gc_edc_config()
1148 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_psm_gc_edc_config()
[all …]
H A Dsmu7_powertune.c963 num_se = adev->gfx.config.max_shader_engines; in smu7_enable_didt_config()
970 adev->gfx.rlc.funcs->enter_safe_mode(adev); in smu7_enable_didt_config()
1017 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_enable_didt_config()
1023 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_enable_didt_config()
1037 adev->gfx.rlc.funcs->enter_safe_mode(adev); in smu7_disable_didt_config()
1049 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_disable_didt_config()
1054 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_disable_didt_config()
/dragonfly/sys/dev/drm/radeon/
H A Dradeon_ucode.h214 struct gfx_firmware_header_v1_0 gfx; member

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