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Searched refs:ixCG_CLKPIN_CNTL_2 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
H A Dsmu_7_1_1_d.h57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
H A Dsmu_7_0_1_d.h57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
H A Dsmu_7_1_2_d.h57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
H A Dsmu_7_1_3_d.h60 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
H A Dsmu_7_1_0_d.h57 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c1665 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in cik_program_aspm()
1668 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
H A Dvi.c334 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk()