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Searched refs:ixCG_DCLK_STATUS (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h38 #define ixCG_DCLK_STATUS 0xc05000a0 macro
H A Dsmu_7_1_1_d.h38 #define ixCG_DCLK_STATUS 0xc05000a0 macro
H A Dsmu_7_0_1_d.h38 #define ixCG_DCLK_STATUS 0xc05000a0 macro
H A Dsmu_7_1_2_d.h38 #define ixCG_DCLK_STATUS 0xc05000a0 macro
H A Dsmu_7_1_3_d.h39 #define ixCG_DCLK_STATUS 0xc05000a0 macro
H A Dsmu_7_1_0_d.h38 #define ixCG_DCLK_STATUS 0xc05000a0 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c1336 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in cik_set_uvd_clocks()
H A Dvi.c781 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()