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Searched refs:ixCG_DISPLAY_GAP_CNTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h709 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
H A Dsmu_7_1_1_d.h993 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
H A Dsmu_7_0_1_d.h1199 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
H A Dsmu_7_1_2_d.h1153 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
H A Dsmu_7_1_3_d.h1055 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
H A Dsmu_7_1_0_d.h1229 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 macro
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c387 ixCG_DISPLAY_GAP_CNTL); in smu7_enable_display_gap()
396 ixCG_DISPLAY_GAP_CNTL, display_gap); in smu7_enable_display_gap()
4064 …nt32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); in smu7_program_display_gap()
4071 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); in smu7_program_display_gap()