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Searched refs:ixCG_DISPLAY_GAP_CNTL2 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h710 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
H A Dsmu_7_1_1_d.h994 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
H A Dsmu_7_0_1_d.h1200 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
H A Dsmu_7_1_2_d.h1154 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
H A Dsmu_7_1_3_d.h1056 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
H A Dsmu_7_1_0_d.h1230 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 macro
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c4092 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); in smu7_program_display_gap()