Searched refs:ixDIDT_SQ_CTRL0 (Results 1 – 9 of 9) sorted by relevance
| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | smu7_powertune.c | 142 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ…
143 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ…
144 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
145 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ…
146 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ…
147 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ…
148 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ…
149 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ…
284 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ…
285 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ…
[all …]
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| H A D | vega10_powertune.c | 210 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL…
211 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFF…
212 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTR…
213 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__D…
214 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DID…
215 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DI…
216 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CT…
217 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0…
218 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_…
219 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DI…
[all …]
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 2507 #define ixDIDT_SQ_CTRL0 0x0 macro
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| H A D | gfx_7_2_d.h | 2532 #define ixDIDT_SQ_CTRL0 0x0 macro
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| H A D | gfx_8_0_d.h | 2777 #define ixDIDT_SQ_CTRL0 0x0 macro
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| H A D | gfx_8_1_d.h | 2755 #define ixDIDT_SQ_CTRL0 0x0 macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 7079 #define ixDIDT_SQ_CTRL0 … macro
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| H A D | gc_9_1_offset.h | 7344 #define ixDIDT_SQ_CTRL0 … macro
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| H A D | gc_9_2_1_offset.h | 7383 #define ixDIDT_SQ_CTRL0 … macro
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