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Searched refs:ixLCAC_MC0_OVR_SEL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h27 #define ixLCAC_MC0_OVR_SEL 0x011D macro
H A Dsmu_8_0_d.h633 #define ixLCAC_MC0_OVR_SEL 0xd0208134 macro
H A Dsmu_7_0_0_d.h726 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_1_d.h1026 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_0_1_d.h1215 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_2_d.h1176 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_1_3_d.h1108 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_1_0_d.h1245 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro