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Searched refs:ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h3598 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL … macro
H A Dnbio_7_0_offset.h4580 #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL … macro