Searched refs:max_clock_voltage_on_dc (Results 1 – 17 of 17) sorted by relevance
822 &pp_table_information->max_clock_voltage_on_dc, pHardLimits); in init_clock_voltage_dependency()824 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()825 pp_table_information->max_clock_voltage_on_dc.sclk; in init_clock_voltage_dependency()826 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()827 pp_table_information->max_clock_voltage_on_dc.mclk; in init_clock_voltage_dependency()828 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()829 pp_table_information->max_clock_voltage_on_dc.vddc; in init_clock_voltage_dependency()830 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()831 pp_table_information->max_clock_voltage_on_dc.vddci; in init_clock_voltage_dependency()
971 &pp_table_info->max_clock_voltage_on_dc, in init_powerplay_extended_tables()974 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()975 pp_table_info->max_clock_voltage_on_dc.sclk; in init_powerplay_extended_tables()976 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()977 pp_table_info->max_clock_voltage_on_dc.mclk; in init_powerplay_extended_tables()978 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()979 pp_table_info->max_clock_voltage_on_dc.vddc; in init_powerplay_extended_tables()980 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()981 pp_table_info->max_clock_voltage_on_dc.vddci; in init_powerplay_extended_tables()
239 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()240 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()241 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
1841 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in smu7_patch_clock_voltage_limits_with_vddc_leakage()1842 table_info->max_clock_voltage_on_dc.vddc; in smu7_patch_clock_voltage_limits_with_vddc_leakage()2037 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); in smu7_complete_dependency_tables()2046 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); in smu7_complete_dependency_tables()2446 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); in smu7_patch_dependency_tables_with_leakage()2913 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in smu7_apply_state_adjust_rules()
1358 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); in init_clock_voltage_dependency()
728 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); in vega10_complete_dependency_tables()3131 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
505 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; member542 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; member601 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; member
2110 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in btc_apply_state_adjust_rules()2240 if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && in btc_apply_state_adjust_rules()2241 (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && in btc_apply_state_adjust_rules()2242 (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)) in btc_apply_state_adjust_rules()2709 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in btc_dpm_init()2710 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in btc_dpm_init()2711 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in btc_dpm_init()
974 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in r600_parse_extended_power_table()977 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in r600_parse_extended_power_table()980 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in r600_parse_extended_power_table()982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in r600_parse_extended_power_table()
861 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()3971 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()4020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()4053 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;4084 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;5116 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()5947 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()5948 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()5949 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()4256 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ni_dpm_init()4257 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ni_dpm_init()4258 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ni_dpm_init()
3027 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()3176 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()7051 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()7052 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()7053 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
1495 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; member
436 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()439 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()442 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()444 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
206 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; member
3486 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()3635 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()7456 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()7457 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()7458 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
2864 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_uvd_smc_table()2900 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_vce_smc_table()