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Searched refs:max_supported_dppclk_khz (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clocks.c495 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; in dcn1_determine_dppclk_threshold()
566 dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in dcn1_ramp_up_dispclk_with_dpp()
/dragonfly/sys/dev/drm/amd/display/dc/
H A Ddc.h204 int max_supported_dppclk_khz; member
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c1065 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
1069 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
1073 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
1077 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c348 dc->current_state->bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()