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Searched refs:mmALPHA_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c2152 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2154 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
H A Ddce_v11_0.c2185 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2187 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h2795 #define mmALPHA_CONTROL 0x1abc macro
H A Ddce_10_0_d.h3574 #define mmALPHA_CONTROL 0x1abc macro
H A Ddce_11_0_d.h3335 #define mmALPHA_CONTROL 0x1abc macro
H A Ddce_11_2_d.h4566 #define mmALPHA_CONTROL 0x1abc macro