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Searched refs:mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dmxgpu_ai.c138 mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0)); in xgpu_ai_mailbox_trans_msg()
141 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h2600 #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 … macro