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Searched refs:mmCGTT_ROM_CLK_CTRL0 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smuio/
H A Dsmuio_9_0_offset.h32 #define mmCGTT_ROM_CLK_CTRL0 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15.c892 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); in soc15_update_rom_medium_grain_clock_gating()
902 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); in soc15_update_rom_medium_grain_clock_gating()
978 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); in soc15_common_get_clockgating_state()