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Searched refs:mmCP_CPC_IC_BASE_CNTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dsmu8_smumgr.c199 mmCP_CPC_IC_BASE_CNTL); in smu8_load_mec_firmware()
205 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); in smu8_load_mec_firmware()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
H A Dgfx_8_1_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2563 #define mmCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_1_offset.h2872 #define mmCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_2_1_offset.h2806 #define mmCP_CPC_IC_BASE_CNTL … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c2559 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_0_cp_compute_load_microcode()