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Searched refs:mmCP_HQD_EOP_CONTROL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v8.c345 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) in kgd_hqd_load()
H A Dgfx_v9_0.c2713 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in gfx_v9_0_mqd_init()
2839 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, in gfx_v9_0_kiq_init_register()
H A Dgfx_v8_0.c4734 tmp = RREG32(mmCP_HQD_EOP_CONTROL); in gfx_v8_0_mqd_init()
4869 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++) in gfx_v8_0_mqd_commit()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h672 #define mmCP_HQD_EOP_CONTROL 0x326c macro
H A Dgfx_8_1_d.h672 #define mmCP_HQD_EOP_CONTROL 0x326c macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2839 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_9_1_offset.h3124 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_9_2_1_offset.h3080 #define mmCP_HQD_EOP_CONTROL … macro