Searched refs:mmCP_HQD_PQ_CONTROL (Results 1 – 10 of 10) sorted by relevance
| /dragonfly/sys/dev/drm/amd/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 1513 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1523 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1533 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
1543 { 0xc8318509, mmCP_HQD_PQ_CONTROL },
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 584 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
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| H A D | gfx_7_2_d.h | 597 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
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| H A D | gfx_8_0_d.h | 647 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
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| H A D | gfx_8_1_d.h | 647 #define mmCP_HQD_PQ_CONTROL 0x3256 macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 2760 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in gfx_v9_0_mqd_init()
2881 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, in gfx_v9_0_kiq_init_register()
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| H A D | gfx_v8_0.c | 4763 tmp = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v8_0_mqd_init()
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2789 #define mmCP_HQD_PQ_CONTROL … macro
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| H A D | gc_9_1_offset.h | 3074 #define mmCP_HQD_PQ_CONTROL … macro
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| H A D | gc_9_2_1_offset.h | 3030 #define mmCP_HQD_PQ_CONTROL … macro
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