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Searched refs:mmCP_HQD_PQ_WPTR_HI (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c434 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
472 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_hqd_load()
516 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_dump()
H A Dgfx_v9_0.c2860 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
2910 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
2962 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_0_kiq_fini_register()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2871 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_9_1_offset.h3156 #define mmCP_HQD_PQ_WPTR_HI … macro
H A Dgc_9_2_1_offset.h3112 #define mmCP_HQD_PQ_WPTR_HI … macro