Home
last modified time | relevance | path

Searched refs:mmCP_HQD_WG_STATE_OFFSET (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h681 #define mmCP_HQD_WG_STATE_OFFSET 0x3275 macro
H A Dgfx_8_1_d.h681 #define mmCP_HQD_WG_STATE_OFFSET 0x3275 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2857 #define mmCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_9_1_offset.h3142 #define mmCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_9_2_1_offset.h3098 #define mmCP_HQD_WG_STATE_OFFSET … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c4841 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); in gfx_v8_0_mqd_init()