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Searched refs:mmCP_ME_RAM_WADDR (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h462 #define mmCP_ME_RAM_WADDR 0x3057 macro
H A Dgfx_7_0_d.h243 #define mmCP_ME_RAM_WADDR 0x3057 macro
H A Dgfx_7_2_d.h245 #define mmCP_ME_RAM_WADDR 0x3057 macro
H A Dgfx_8_0_d.h274 #define mmCP_ME_RAM_WADDR 0xf816 macro
H A Dgfx_8_1_d.h275 #define mmCP_ME_RAM_WADDR 0xf816 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c2382 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); in gfx_v9_0_cp_gfx_load_microcode()
2385 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
H A Dgfx_v8_0.c4336 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v8_0_cp_gfx_load_microcode()
4339 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6665 #define mmCP_ME_RAM_WADDR … macro
H A Dgc_9_1_offset.h6946 #define mmCP_ME_RAM_WADDR … macro
H A Dgc_9_2_1_offset.h6974 #define mmCP_ME_RAM_WADDR … macro