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Searched refs:mmCP_MQD_CONTROL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h601 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_7_2_d.h614 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_8_0_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
H A Dgfx_8_1_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c2750 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v9_0_mqd_init()
2871 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, in gfx_v9_0_kiq_init_register()
H A Dgfx_v8_0.c4753 tmp = RREG32(mmCP_MQD_CONTROL); in gfx_v8_0_mqd_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2829 #define mmCP_MQD_CONTROL … macro
H A Dgc_9_1_offset.h3114 #define mmCP_MQD_CONTROL … macro
H A Dgc_9_2_1_offset.h3070 #define mmCP_MQD_CONTROL … macro