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Searched refs:mmCP_RB0_BASE (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h494 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_7_0_d.h195 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_7_2_d.h195 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_8_0_d.h219 #define mmCP_RB0_BASE 0x3040 macro
H A Dgfx_8_1_d.h220 #define mmCP_RB0_BASE 0x3040 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2320 #define mmCP_RB0_BASE … macro
H A Dgc_9_1_offset.h2634 #define mmCP_RB0_BASE … macro
H A Dgc_9_2_1_offset.h2572 #define mmCP_RB0_BASE … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c2493 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v8_0.c4513 WREG32(mmCP_RB0_BASE, rb_addr); in gfx_v8_0_cp_gfx_resume()