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Searched refs:mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_d.h9780 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x4924 macro
H A Ddce_12_0_offset.h12518 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h11135 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE … macro