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Searched refs:mmDP3_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_resource.c88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_resource.c94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
H A Ddce112_resource.c89 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4560 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc macro
H A Ddce_11_2_d.h5792 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc macro
H A Ddce_12_0_offset.h11152 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9369 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro