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Searched refs:mmDP4_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_resource.c89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC macro
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_resource.c95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC macro
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
H A Ddce112_resource.c90 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4561 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc macro
H A Ddce_11_2_d.h5793 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc macro
H A Ddce_12_0_offset.h11436 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9679 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL … macro