Searched refs:mmDPG_WATERMARK_MASK_CONTROL (Results 1 – 7 of 7) sorted by relevance
/dragonfly/sys/dev/drm/amd/display/dc/dce80/ |
H A D | dce80_resource.c | 116 - mmDPG_WATERMARK_MASK_CONTROL), 122 - mmDPG_WATERMARK_MASK_CONTROL), 128 - mmDPG_WATERMARK_MASK_CONTROL), 134 - mmDPG_WATERMARK_MASK_CONTROL), 140 - mmDPG_WATERMARK_MASK_CONTROL), 146 - mmDPG_WATERMARK_MASK_CONTROL),
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 1111 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks() 1113 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks() 1120 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks() 1126 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
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H A D | dce_v11_0.c | 1137 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks() 1139 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks() 1146 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks() 1152 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
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/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/ |
H A D | dce_8_0_d.h | 5180 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
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H A D | dce_10_0_d.h | 6393 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
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H A D | dce_11_0_d.h | 6516 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
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H A D | dce_11_2_d.h | 7814 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
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