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Searched refs:mmDPG_WATERMARK_MASK_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce80/
H A Ddce80_resource.c116 - mmDPG_WATERMARK_MASK_CONTROL),
122 - mmDPG_WATERMARK_MASK_CONTROL),
128 - mmDPG_WATERMARK_MASK_CONTROL),
134 - mmDPG_WATERMARK_MASK_CONTROL),
140 - mmDPG_WATERMARK_MASK_CONTROL),
146 - mmDPG_WATERMARK_MASK_CONTROL),
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1111 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1113 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1120 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1126 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
H A Ddce_v11_0.c1137 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1139 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1146 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1152 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5180 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_10_0_d.h6393 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_11_0_d.h6516 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_11_2_d.h7814 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro