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Searched refs:mmDSICLK_CGTT_BLK_CTRL_REG (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h486 #define mmDSICLK_CGTT_BLK_CTRL_REG … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h678 #define mmDSICLK_CGTT_BLK_CTRL_REG … macro