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Searched refs:mmGB_MACROTILE_MODE0 (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c1002 {mmGB_MACROTILE_MODE0},
1098 case mmGB_MACROTILE_MODE0: in cik_get_register_value()
1114 idx = (reg_offset - mmGB_MACROTILE_MODE0); in cik_get_register_value()
H A Dvi.c527 {mmGB_MACROTILE_MODE0},
622 case mmGB_MACROTILE_MODE0: in vi_get_register_value()
638 idx = (reg_offset - mmGB_MACROTILE_MODE0); in vi_get_register_value()
H A Dgfx_v8_0.c2411 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2601 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2790 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2993 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3195 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3366 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3542 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h724 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_7_2_d.h737 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_8_0_d.h809 #define mmGB_MACROTILE_MODE0 0x2664 macro
H A Dgfx_8_1_d.h809 #define mmGB_MACROTILE_MODE0 0x2664 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1002 #define mmGB_MACROTILE_MODE0 … macro
H A Dgc_9_1_offset.h976 #define mmGB_MACROTILE_MODE0 … macro
H A Dgc_9_2_1_offset.h942 #define mmGB_MACROTILE_MODE0 … macro