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Searched refs:mmGC_USER_SHADER_ARRAY_CONFIG (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h692 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_7_0_d.h2338 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_7_2_d.h2362 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_8_0_d.h2602 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
H A Dgfx_8_1_d.h2581 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c4838 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v9_0_set_user_cu_inactive_bitmap()
4846 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v9_0_get_cu_active_bitmap()
H A Dgfx_v8_0.c7371 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v8_0_set_user_cu_inactive_bitmap()
7379 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v8_0_get_cu_active_bitmap()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h316 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro
H A Dgc_9_1_offset.h312 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro
H A Dgc_9_2_1_offset.h306 #define mmGC_USER_SHADER_ARRAY_CONFIG … macro