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Searched refs:mmGDS_OA_VMID0 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2265 #define mmGDS_OA_VMID0 0x3330 macro
H A Dgfx_7_2_d.h2287 #define mmGDS_OA_VMID0 0x3330 macro
H A Dgfx_8_0_d.h2485 #define mmGDS_OA_VMID0 0x3330 macro
H A Dgfx_8_1_d.h2464 #define mmGDS_OA_VMID0 0x3330 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3077 #define mmGDS_OA_VMID0 … macro
H A Dgc_9_1_offset.h3364 #define mmGDS_OA_VMID0 … macro
H A Dgc_9_2_1_offset.h3314 #define mmGDS_OA_VMID0 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c3422 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, in gfx_v9_0_ring_emit_gds_switch()
H A Dgfx_v8_0.c175 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},