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Searched refs:mmGDS_VMID0_SIZE (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c1318 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_ngg_init()
1423 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), in gfx_v9_0_ngg_en()
1440 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); in gfx_v9_0_ngg_en()
3412 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v9_0_ring_emit_gds_switch()
4802 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_set_gds_init()
H A Dgfx_v8_0.c175 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
7335 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2233 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_7_2_d.h2255 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_8_0_d.h2453 #define mmGDS_VMID0_SIZE 0x3301 macro
H A Dgfx_8_1_d.h2432 #define mmGDS_VMID0_SIZE 0x3301 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2983 #define mmGDS_VMID0_SIZE … macro
H A Dgc_9_1_offset.h3270 #define mmGDS_VMID0_SIZE … macro
H A Dgc_9_2_1_offset.h3220 #define mmGDS_VMID0_SIZE … macro