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Searched refs:mmGDS_VMID5_BASE (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2222 #define mmGDS_VMID5_BASE 0x330a macro
H A Dgfx_7_2_d.h2244 #define mmGDS_VMID5_BASE 0x330a macro
H A Dgfx_8_0_d.h2442 #define mmGDS_VMID5_BASE 0x330a macro
H A Dgfx_8_1_d.h2421 #define mmGDS_VMID5_BASE 0x330a macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3001 #define mmGDS_VMID5_BASE … macro
H A Dgc_9_1_offset.h3288 #define mmGDS_VMID5_BASE … macro
H A Dgc_9_2_1_offset.h3238 #define mmGDS_VMID5_BASE … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c180 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},