Home
last modified time | relevance | path

Searched refs:mmGPU_HDP_FLUSH_DONE (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dnbio_v7_0.c245 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_0_get_hdp_flush_done_offset()
H A Dsdma_v2_4.c284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
H A Dsdma_v3_0.c459 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
H A Dgfx_v8_0.c6341 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v8_0_ring_emit_hdp_flush()
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_d.h72 #define mmGPU_HDP_FLUSH_DONE 0x1538 macro
H A Dbif_5_0_d.h78 #define mmGPU_HDP_FLUSH_DONE 0x1538 macro
H A Dbif_5_1_d.h71 #define mmGPU_HDP_FLUSH_DONE 0x1538 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1129 #define mmGPU_HDP_FLUSH_DONE … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4480 #define mmGPU_HDP_FLUSH_DONE … macro