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Searched refs:mmGPU_HDP_FLUSH_REQ (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dnbio_v7_0.c240 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_0_get_hdp_flush_req_offset()
H A Dsdma_v2_4.c285 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in sdma_v2_4_ring_emit_hdp_flush()
H A Dsdma_v3_0.c460 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in sdma_v3_0_ring_emit_hdp_flush()
H A Dgfx_v8_0.c6340 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v8_0_ring_emit_hdp_flush()
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_d.h71 #define mmGPU_HDP_FLUSH_REQ 0x1537 macro
H A Dbif_5_0_d.h77 #define mmGPU_HDP_FLUSH_REQ 0x1537 macro
H A Dbif_5_1_d.h70 #define mmGPU_HDP_FLUSH_REQ 0x1537 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1127 #define mmGPU_HDP_FLUSH_REQ … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4478 #define mmGPU_HDP_FLUSH_REQ … macro