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Searched refs:mmMAILBOX_MSGBUF_TRN_DW0 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dmxgpu_vi.c357 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
360 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); in xgpu_vi_mailbox_trans_msg()
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h177 #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1133 #define mmMAILBOX_MSGBUF_TRN_DW0 … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h4484 #define mmMAILBOX_MSGBUF_TRN_DW0 … macro