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Searched refs:mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_offset.h1751 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro
H A Dmmhub_9_1_offset.h1783 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro
H A Dmmhub_9_3_0_offset.h1767 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5896 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro
H A Dgc_9_1_offset.h6175 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro
H A Dgc_9_2_1_offset.h6139 #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … macro