Home
last modified time | relevance | path

Searched refs:mmPA_CL_UCP_0_W (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h812 #define mmPA_CL_UCP_0_W 0xA172 macro
H A Dgfx_7_0_d.h927 #define mmPA_CL_UCP_0_W 0xa172 macro
H A Dgfx_7_2_d.h940 #define mmPA_CL_UCP_0_W 0xa172 macro
H A Dgfx_8_0_d.h1022 #define mmPA_CL_UCP_0_W 0xa172 macro
H A Dgfx_8_1_d.h1022 #define mmPA_CL_UCP_0_W 0xa172 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h3757 #define mmPA_CL_UCP_0_W … macro
H A Dgc_9_1_offset.h4044 #define mmPA_CL_UCP_0_W … macro
H A Dgc_9_2_1_offset.h3994 #define mmPA_CL_UCP_0_W … macro