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Searched refs:mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h2281 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX macro
H A Dnbio_7_0_offset.h4165 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX macro