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Searched refs:mmPHYPLLD_PIXCLK_RESYNC_CNTL (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_d.h1072 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x103 macro
H A Ddce_12_0_offset.h656 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h470 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL … macro