Searched refs:mmPWR_MISC_CNTL_STATUS (Results 1 – 2 of 2) sorted by relevance
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | smu10_hwmgr.c | 45 #define mmPWR_MISC_CNTL_STATUS 0x0183 macro 291 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); in smu10_is_gfx_on()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfx_v9_0.c | 48 #define mmPWR_MISC_CNTL_STATUS 0x0183 macro 2021 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); in pwr_10_0_gfxip_control_over_cgpg() 2026 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg() 2032 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg() 2037 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); in pwr_10_0_gfxip_control_over_cgpg()
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