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Searched refs:mmRLC_GPM_TIMER_INT_3 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5933 #define mmRLC_GPM_TIMER_INT_3 … macro
H A Dgc_9_1_offset.h6212 #define mmRLC_GPM_TIMER_INT_3 … macro
H A Dgc_9_2_1_offset.h6176 #define mmRLC_GPM_TIMER_INT_3 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c2246 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); in gfx_v9_0_rlc_start()