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Searched refs:mmRLC_GPM_UTCL1_CNTL_1 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6159 #define mmRLC_GPM_UTCL1_CNTL_1 macro
H A Dgc_9_1_offset.h6438 #define mmRLC_GPM_UTCL1_CNTL_1 macro
H A Dgc_9_2_1_offset.h6414 #define mmRLC_GPM_UTCL1_CNTL_1 macro